Are we on schedule?
A good information found while serfing on internet, want to share with other ITVidya members..
Cadence solution addresses the rising variance in planned schedule versus actual schedule in a chip design project aka ''schedule predictability crisis''
Front-end logic design is a major component of any chip design project. Use of legacy tools and technologies in logic design and exponentially growing design complexity and challenges has lead to a crisis in the schedule predictability of chip programs. Power efficiency, growing design/verification gap, a logical-physical modeling gap amongst others have lead to variability in product development that is as much as the schedule itself, in many cases.
US based electronic-design innovation company Cadence has recently announced Logic Design Team Solution to address the front-end design predictability crisis.
"The schedule predictability crisis is the problem of no longer being able to have any degree of accuracy in the prediction of how long a chip design project will take. The measured variance in original planned schedule versus actual schedule, for highly complex designs, shows the variance to be as great as the original schedule, clearly this is a crisis in the highly competitive world of chip design," informed Michal Siwinski, Director, Cadence Design Systems, Inc. in an exclusive discussion with CIOL.
According to Michal, Cadence solution addresses this crisis by providing automation for a metric-driven methodology that enables continuous monitoring of all key program vital signs. Along with automated design management functionality, there are new technology integrations across key design technologies to bridge gaps that formerly were the source of surprises that caused decreases in predictability.
Offering the first set of integrated components to enable schedule predictability in RTL design, the Cadence Logic Design Solution offers logic design teams key "Design with" elements-spanning design verification, power, test, and physical-which include:
Design with Verification - enables early design verification
Design with Power - enables power-aware design and verification
Design with Physical - designer-level physical prototyping
Design with Test - test-aware early front-end design
Design Logical Signoff - front-end to back-end logical handoff
Design Management - plan- and metrics-driven front-end design management
The new power design management capabilities provide, a power plan infrastructure defining a set of metrics for predictable power closure; automated tracking and measurements of dynamic and leakage power analysis during synthesis; automated validation of level shifters, isolation cells, power gating and other power management techniques; an aggregation of power metrics from Encounter RTL Compiler, Encounter Conformal, and Encounter Test; SystemVerilog support across the front-end flow, including design, assertions, and test bench etc.
Talking on the maturity of Indian market for such tools, Michal opines, "The market for front-end design solutions is one of the fastest growing in the world. Any digital design team tackling designs at 90nm and below will derive tremendous benefits from this solution. India is gaining recognition as a center of design excellence, and is being rewarded with the 'opportunity' to tackle some of the most challenging design projects in the world. Gaining expertise in the newest methods of logic design will have rippling benefits throughout the functional validation and physical implementation flows as well. If these new methods are quickly embraced, design teams in India can distinguish themselves by delivering higher quality design results in less time, on very complex design problems."
There are other players in this space, however Cadence is the only EDA vendor with the breadth and depth of solutions to address the predictability challenges faced by design teams.
The solution is available in India in many versions and training on product usage is also available.
Regards,
Nikhil Kale
