Design Verification Methodologies Workshop (April 5-6, 2007, Pune)

Third Design Verification Methodologies Workshop
April 5-6, 2007
I2IT Pune Campus, Maharashtra

Organized by VLSI Society of India and
International Institute of Information Technology, Pune

I2IT Pune
http://www.isquarei t.ac.in/

Supported by IEEE Pune Subsection

Corporate Sponsor
Wipro Technologies, Pune

Background:

Nanotechnologies have ushered in System-On-Chip designs with 50 million gates. Functional and timing verification of such designs is a formidable task. Design Verification has been known to be biggest contributor to the design cycle time. Statistics also indicate that design respins are often due to functional bugs detected late. Cutting down the time for verification is one of the major goals of design teams
across the globe. Many new methodologies have emerged towards solving this problem. This two-day workshop is intended as a forum to discuss the new trends and methodologies for Design Verification. It is also a forum to share current practices in Design Verification.

Workshop History:

The first workshop in this series was held on November 25, 2005 at Hotel
Atria, Bangalore and was attended by about 60 professionals. The details
of the previous workshop can be found at:
http://vlsi- india.org/ vsi/activities/ 2007/dvw05_ blr

The second workshop was held during March 24-25, 2006 at Wipro
Technologies, Pune and was attended by about 60 professionals. The
details of the previous workshop can be found at:
http://vlsi- india.org/ vsi/activities/ 2007/dvm06_ pne

The workshop is suitable for practitioners of Design Verification and
for students/faculty who are engaged in VLSI design projects.

Venue

International Institute of Information Technology (I2IT, Pune)
Microelectronics and VLSI, I2IT, Pune
P-14, Rajiv Gandhi Infotech Park, Hinjewadi
Pune 411057, Maharashtra
Phone: 020-22933441 FAX: 020-22934191 (Contact: Prof. Sheetal Bhandari)

DVM 2007 Speakers

Dr. P.P.Chakrabarti - IIT Kharagpur

Tarun Garg, Cadence Design Systems

Shanthamoorthi Velusamy, Wipro Technologies

Haridas V., SoC Design Technology, NXP Semiconductors Indi
Dr.Kaushik De, Verification Business Unit, Synopsys India

Desingh D Balasubramanian, Poseidon-Systems India

Intel India

Dr. Supratik Chakraborty - IIT Bombay

Aditya Kher, Synopsys India

Manikandan Panchapakesan, NXP Semicondutors India

Vishwanath B and Ankush Jain, NXP Semicondutors India

Bhaskar Karmakar, Texas Instruments India

Mrinal Das, Sankalp Semiconductor

Local Organizing Committee:

Prof. Sheetal U. Bhandari, I2IT Pune

Prof. Manish Malojirao Patil, I2IT Pune

Ramakant Kapatral, Wipro Technologies, Pune