Chip Designing

A good information found while serfing on internet, want to share with other ITVidya members..

Cadence solution addresses the rising variance in planned schedule versus actual schedule in a chip design project aka ''schedule predictability crisis''

Front-end logic design is a major component of any chip design project. Use of legacy tools and technologies in logic design and exponentially growing design complexity and challenges has lead to a crisis in the schedule predictability of chip programs. Power efficiency, growing design/verification gap, a logical-physical modeling gap amongst others have lead to variability in product development that is as much as the schedule itself, in many cases.